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Project Coordinator


 

Dr Georg Stettinger

 
Infineon Technologies AG
81726 München
Germany

Bits, Flips and RISCs

Nicolas Gerlin, Endri Kaja, Fabian Vargas, Li Lu, Anselm Breitenreiter, Junchao Chen, Markus Ulbricht, Maribel Gomez, Ares Tahiraga, Sebastian Prebeck, Eyck Jentzsch, Milos Krstic, Wolfgang Ecker

Abstract: Electronic systems can be submitted to hostile environments leading to bit-flips or stuck-at faults and, ultimately, a system malfunction or failure. In safety-critical applications, the risks of such events should be managed to prevent injuries or material damage. This paper provides a comprehensive overview of the challenges associated with designing and verifying safe and reliable systems, as well as the potential of the RISC-V architecture in addressing these challenges.We present several state-of-the-art safety and reliability verification techniques in the design phase. These include a highly-automated verification flow, an automated fault injection and analysis tool, and an AI-based fault verification flow. Furthermore, we discuss core hardening and fault mitigation strategies at the design level. We focus on automated SoC hardening using model-driven development and resilient processing based on sensing and prediction for space and avionic applications.By combining these techniques with the inherent flexibility of the RISC-V architecture, designers can develop tailored solutions that balance cost, performance, and fault tolerance to meet the requirements of various safety-critical applications in different safety domains, such as avionics, automotive, and space. The insights and methodologies presented in this paper contribute to the ongoing efforts to improve the dependability of computing systems in safety-critical environments.


Bits, Flips and RISCs


 

Acknowledgement

ArchitectECA2030 has been accepted for funding within (ECSEL JU) in collaboration with the European Union’s H2020 Framework Programs under grant agreement No 877539.

The project will receive an ECSEL JU funding up to 4 M€ completed with national budgets from national funding authorities in Germany, Netherlands, Czech Republic, Austria and Norway.  

Project Facts

Short Name: ArchitectECA2030

Full Name: Trustable architectures with acceptable residual risk for the electric, connected and automated cars

Duration:  01/07/2020- 30/06/2023

Total Costs: ~ € 13,6 Mio.

Consortium: 20 partners from 8 countries

Coordinator: Infineon Technologies AG

Funding

 

Horizon 2020
Horizon 2020

 

    

National Funding

National Funding

 


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